In recent years, in a display device such as a liquid crystal display device, providing a gate driver (a scanning signal line drive circuit) for driving gate bus lines (scanning signal lines) in a monolithic manner has been more common. Conventionally, a gate driver is in many cases mounted at the periphery of a substrate which forms a display panel, as an IC (Integrated Circuit) chip. However, in recent years, a case in which the gate driver is directly formed on the substrate has been gradually increasing. Such a gate driver is called a “monolithic gate driver”, etc. In a display device including a monolithic gate driver, conventionally, a thin film transistor using amorphous silicon (a-Si) is typically adopted as a drive element. However, in recent years, a thin film transistor using polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (e.g., an indium gallium zinc oxide), etc., has started to be adopted as a drive element. Particularly, by adopting a thin film transistor using an oxide semiconductor as a drive element, low power consumption and high definition are achieved.
Meanwhile, in a display unit of an active matrix-type display device there are formed pixel circuits including a plurality of source bus lines (video signal lines); a plurality of gate bus lines; and a plurality of pixel formation portions provided at the respective intersections of the plurality of source bus lines and the plurality of gate bus lines. The plurality of pixel formation portions are arranged in a matrix form and thereby form a pixel array. For example, in a liquid crystal display device, each pixel formation portion includes a thin film transistor which is a switching element connected at its gate terminal to a gate bus line passing through a corresponding intersection, and connected at its source terminal to a source bus line passing through the intersection; a pixel capacitance for holding a pixel voltage value; and the like. In addition, the liquid crystal display device is provided with the above-described gate driver and a source driver (video signal line drive circuit) for driving the source bus lines.
A video signal representing a pixel voltage value is transmitted through a source bus line. Each source bus line cannot transmit video signals representing pixel voltage values for a plurality of rows at the same time (simultaneously). Due to this, writing (charging) of video signals to the pixel capacitances in the above-described pixel formation portions arranged in a matrix form is sequentially performed row by row. Hence, the gate driver is composed of a shift register circuit including a plurality of stages so that the plurality of gate bus lines can be sequentially selected for a predetermined period of time. Then, by sequentially outputting active scanning signals from the respective stages of the shift register circuit (hereinafter, a circuit that forms each stage of the shift register circuit is referred to as a “unit circuit”), writing of video signals to the pixel capacitances is sequentially performed row by row as described above.
FIG. 21 is a circuit diagram showing the simplest configuration of a conventional unit circuit. The unit circuit includes four thin film transistors M81 to M84 and one bootstrap capacitor Cb. In addition, the unit circuit has three input terminals 81 to 83 and one output terminal 88, in addition to input terminals for a low-level direct-current power supply potential VSS. Here, an input terminal that receives an input signal S is provided with reference character 81, an input terminal that receives a clock signal CKA is provided with reference character 82, an input terminal that receives a reset signal R is provided with reference character 83, and an output terminal that outputs an output signal Q is provided with reference character 88. A source terminal of the thin film transistor M81, a drain terminal of the thin film transistor M82, a gate terminal of the thin film transistor M83, and one end of the bootstrap capacitor Cb are connected to each other. Note that a region (wiring line) in which they are connected to each other is referred to as an “internal node”. The internal node is provided with reference character VC.
In a configuration such as that described above, when the clock signal CKA changes from a low level (off level) to a high level (on level) with the internal node VC being precharged, the potential of the internal node VC greatly increases due to the bootstrapping effect by the bootstrap capacitor Cb, by which a large voltage is applied to the gate terminal of the thin film transistor M83. By this, the high-level clock signal CKA passes through the thin film transistor M83 and is provided to the output terminal 88, with its level maintained. In this manner, a gate bus line connected to the output terminal 88 of the unit circuit goes into a selected state.
However, since the clock signal CKA repeats clock operation, noise of the clock signal CKA (clock noise) may get mixed in the internal node VC due to the presence of a parasitic capacitance in the thin film transistor M83 during a period (hereinafter, referred to as an “unselected period”) during which the gate bus line connected to the output terminal 88 of the unit circuit should be maintained in an unselected state. When the potential of the internal node VC increases thereby, a leakage current flows through the thin film transistor M83, increasing the potential of the output terminal 88. As a result, defective operation occurs.
In view of this, in general, in order to prevent the occurrence of defective operation, circuit elements for drawing the potential of the internal node VC and the potential of the output terminal 88 to a low level at appropriate timing are provided in the unit circuit. However, in recent years, there has been growing demand for high definition and a narrow picture-frame. For example, implementation of a high-definition panel with a resolution over 400 ppi and a narrow picture-frame panel with a picture frame less than 1 mm is sought. In view of this, a configuration such as that shown in FIG. 22 is proposed as a configuration of a unit circuit (of a shift register circuit) that takes measures against clock noise with a relatively small number of circuit elements.
A unit circuit shown in FIG. 22 is characterized by including a thin film transistor M94 that controls an electrical connection state between an internal node VC and an output terminal 98 based on a clock signal CKA; and a thin film transistor M93 that controls an electrical connection state between the internal node VC and an input terminal 91 based on a clock signal CKB of the opposite phase to the clock signal CKA. In such a configuration, during a period during which the clock signal CKA is at a high level, the thin film transistor M94 goes into an on state and the internal node VC and the output terminal 98 go into an electrically connected state. In addition, during a period during which the clock signal CKA is at a low level, the thin film transistor M93 goes into an on state and the internal node VC and the input terminal 91 go into an electrically connected state. In this manner, an increase in the potential of the internal node VC caused by clock noise is suppressed.